1. Technical Field
The present disclosure relates to bus arbitration, and more particularly to a bus arbiter, a bus device and a system that implements the bus arbitration.
2. Discussion of the Related Art
A bus arbiter performs bus arbitration between multiple master devices connected to a bus. Each master device outputs a request signal to the bus arbiter. The request signal indicates a request to use the bus. The bus arbiter receives the request signal from the master device, and outputs a grant signal to the master device in a predetermined order. The grant signal indicates a grant for the use of the bus. The master device receiving the grant signal transfers a transaction through the bus to a slave device.
If the multiple master devices simultaneously request the use of the bus, transactions that are successively requested by a single master device may not be successively transferred to the slave device. When the transactions of the master device are not successively transferred, the data processing speed of the slave device may be reduced. In particular, if the slave device is a memory device, the page hit rate of the memory device may be reduced. Even if the master device successively requests transactions for reading or writing data corresponding to adjacent addresses on the same memory page, a transaction of another master device may be inserted between the transactions of the master device, and thus the memory device may receive transactions for reading or writing data on different memory pages. Accordingly, the page hit rate and the data processing speed of the memory device may be reduced. Further, since the data processing speed of the entire system depends upon the data processing speed of the memory device, system performance may be impacted when transactions are not successively transferred to the memory device.